Conventionally, a metal oxide semiconductor field effect transistor (MOSFET) is known as a semiconductor device having a switching function (see, for example, Patent Document 1). The Patent Document 1 discloses a trench gate MOSFET (semiconductor device) in which a gate electrode is embedded in a trench formed in a semiconductor layer.
FIG. 9 is a cross sectional view illustrating a structure of a conventional MOSFET (semiconductor device) disclosed in the Patent Document 1. With reference to FIG. 9, the conventional MOSFET (semiconductor device) includes an n+ type semiconductor substrate 101 and an epitaxial layer (semiconductor layer) 102 formed on the upper surface of the semiconductor substrate 101. This epitaxial layer 102 includes an n− type impurity region (drain region) 102a, a p type impurity region 102b and an n+ type impurity region (source region) 102c formed in this order from the semiconductor substrate 101 side.
In addition, the epitaxial layer 102 is provided with a trench 103 that is formed so as to penetrate the n+ type impurity region 102c and the p type impurity region 102b and to reach a halfway depth of the n− type impurity region 102a. A gate electrode 105 is embedded in the trench 103 via a gate insulator film 104. In addition, an interlayer insulator film 106 is formed on the upper surface of the epitaxial layer 102 so as to close the opening end of the trench 103.
In addition, a source electrode 107 is formed on the upper surface of the epitaxial layer 102 so as to cover the interlayer insulator film 106. In addition, a drain electrode 108 is formed on the back surface of the semiconductor substrate 101.
In the conventional MOSFET having the above-mentioned structure, applied voltage to the gate electrode 105 is changed for on-off control.
Specifically, when a predetermined positive potential is applied to the gate electrode 105, minority carrier (electrons) in the p type impurity region 102b is attracted to the trench 103 side, and an inversion layer 109 is formed, which connects the n− type impurity region (drain region) 102a with the n+ type impurity region (source region) 102c. Thus, current can flow between the source electrode 107 and the drain electrode 108 via the inversion layer 109. As a result, the MOSFET is turned on.
In this way, in the conventional MOSFET, the inversion layer 109, which is formed so as to connect the n− type impurity region (drain region) 102a with the n+ type impurity region (source region) 102c, is made to function as a channel.
In addition, when the application of the predetermined positive potential to the gate electrode 105 is stopped from the above-mentioned state, the inversion layer (channel) 109 disappears so that the current flowing between the source electrode 107 and the drain electrode 108 can be interrupted. As a result, the MOSFET is turned off.
Patent Document 1: JP-A-2001-7149